1. Field of the Invention
This invention relates to a packaging process, and more particularly, to an underfilling method for a flip-chip packaging process.
2. Description of Related Art
It has been a goal of semiconductor manufacturers to develop and a semiconductor integrated circuit(IC) device of a higher integration, while physically downsizing the IC device. A higher-integration, or a higher-density, IC device results in more bonding pads and requires more electrical connections. The packaging techniques for integrated IC have been improved according to the increasing integration of IC devices since the beginning of the semiconductor industry in the early 60s. The wire bonding packaging techniques, such as metal can-type, dual in-line packaging (DIP), can no longer meet the packaging needs of a high-integration IC, taking into consideration the large number of electrical connections and the arrangement of those electrical connections. On the other hand, the techniques that do not apply wire bonding packaging techniques, such as the tape-automated bonding technique, and the flip-chip packaging which was first introduced by IBM in 1964, are still used by the industrial nowadays for packaging a highly integrated IC device. The flip-chip packaging process, because it allows high input/output density, improves electrical performance, is self-aligned, and has a low cost potential, has become a trend for packaging a high-integration IC.
A conventional flip-chip packaging process includes a bumping process, a die-sawing process, a flip-chip process, and an underfilling process, as shown in FIGS. 1A through 1C. Referring to FIG. 1A, a number of metal bumps 106 are formed on pads 102 located on a provided substrate 100. The pads and a passivation layer 104 are formed on the substrate 100 before the bumping process, wherein the passivation layer 104 covers the substrate 100 and expose the pads 102. Since the bumps 106 don""t completely fill the space over the pads 102 in the passivation layer 104, there are some extra spaces 105 between the bumps 106 and the passivation layer 104.
Referring to FIG. 1B, a polishing process is performed to remove the top portion of the bumps 106 to make all the bumps 106 the same height in height, and additionally, to increase the tip areas 107. The height H 109 of the portion of the bumps 106 above the top surface of the passivation layer 104 is still greater than zero after the polishing process. A die-sawing process is performed on the substrate 100 to separate each individual die from the processed wafer.
Referring to FIG. 1C, a flip-chip process is performed by picking up each separated die 120, turning the die 120 over, and attaching the die 120 to a desired position on a target substrate 110 which contains pre-formed connectors 112. By applying a high-temperature environment and proper stress on the die 120, the bumps 106 melt and adhere to the desired substrate 110. In order to dissipate the stress and improve the fatigue life caused by the coefficient of thermal expanding (CTE) mismatch on the bumps 106 and adhesive, an underfill material 114 is introduced into the area between the die 120 and the adhered substrate 110. The exposed surfaces on the pads 102 can also be protected by filling underfill material 114 into the spaces 105.
However, the foregoing conventional flip-chip packaging process still has several drawbacks, such as requiring a long process time and air-trapping problems, so the yield is limited. In a conventional underfilling process, because the underfill material 114 is introduced into the space between the die 120 and the adhered substrate 110 from the edges of the die 120, air tends toward being trapped between the die 120 and the adhered substrate 110. Different underfill dispense patterns developed to resolve the air-trapping problem improve the air-trapping problem, but those underfill dispense patterns are very time-consuming which limits the yield in another way.
It is therefore an objective of the present invention to provide an underfilling method for a flip-chip packaging process including coating a layer of underfill material on a substrate before the die-sawing process to eliminate the air-trapping problem and simplify the underfilling process.
In accordance with the foregoing and other objectives of the present invention, a layer of an underfill material is coated on the passivation layer before the die-sawing process, so that the air-trapping problem can be eliminated and the process time is shortened.